Conventionally, a dual-damascene method has been known as a technique in which after a wiring groove is formed on an insulation film and a via is formed on the bottom of the wiring groove, a conductive material is filled into the wiring groove and the via so as to form a wiring and a contact portion at the same time. In the dual-damascene method, a so-called first-trench system is known (see, Patent Document 1, for example). In the first-trench system, a via pattern is formed on a hard mask by a lithography technique, then a via and a wiring groove are formed by etching. At this time, a wiring pattern has been previously formed on the hard mask.
Configurations of a wiring and a via in the dual-damascene method with the conventional first-trench system are described with reference to FIG. 25. FIG. 25(a) is a plan view illustrating arrangement positions and shapes of a wiring and a via under the wiring. FIG. 25(b) is a plan view illustrating a shape of the wiring only. FIG. 25(c) is a plan view illustrating a shape of a via pattern used when a via mask is formed at manufacturing a semiconductor device. FIG. 25(d) is a plan view illustrating a shape of the via only. FIG. 25(e) is a cross sectional view illustrating a cross section cut along a line A1-A1′ of the plan view in FIG. 25(a). FIG. 25(f) is a cross sectional view illustrating a cross section cut along a line A2-A2′ of the plan view in FIG. 25(a).
As shown in FIGS. 25(a) to 25(d), if a semiconductor substrate is viewed planarly in the direction vertical to the substrate from the top, a substantial overlapped portion of a via pattern 4 and a wiring 1 corresponds to a planar shape of a via 31 to be formed. In FIG. 25(a), since the via 31 is located under the wiring 1, the via 31 is shown by a dotted line.
A shape of a cross section of the via 31 is simply described with reference to FIGS. 25(e) and 25(f). In the dual-damascene method, a wiring formation hard mask 203 is formed on an insulation film 201 located above a lower layer wiring 200, then, a via formation resist mask 204 is formed on the wiring formation hard mask 203. At this time, a wiring pattern 202 has been formed on the wiring formation hard mask 203 and a via pattern 4 has been formed on the via formation resist mask 204. Thereafter, the insulation film 201 is etched by using the via formation resist mask 204 to form a via portion 206 so as to be extended in the depth direction. Further, after the via formation resist mask 204 is removed, the insulation film 201 is etched by using the wiring formation hard mask 203 so as to form a wiring portion 205 so as to be extended in the depth direction. The wiring 1 and the via 31 are simultaneously formed by filling the wiring portion 205 and the via portion 206 with a metal at once.
In a semiconductor manufacturing process, a minimum dimension of the width of a wiring pattern and that of a via pattern are defined conventionally. In a micro fabrication process in recent years, a resolution of the wiring pattern is higher than that of the via pattern so that the minimum dimension of the wiring pattern 202 is smaller than that of the via pattern 4 due to a technical constraint of a manufacturing apparatus. Therefore, a finished planar shape of the via 31 formed under the wiring having the width of minimum dimension corresponds to a substantial overlapped portion of the via pattern 4 having a circular shape and the wiring 1 having the width narrower than a diameter of the via pattern 4 by forming the via with self alignment in the dual-damascene method.
In the layout design of LSI using a placement and routing tool with on-grid design scheme, a plurality of terminals which are capable of transmitting an input signal and an output signal of a basic cell are located at the intersections of wiring grids lined in the X direction and those lined in the Y direction (see Patent Document 2, for example). In order to ensure a wiring resource in an arrangement wiring, via has had a tendency to be arranged near the intersections of wiring grids lined in the X direction and those lined in the Y direction. It is to be noted that the X direction denotes a direction along a power-source wiring of a basic cell while the Y direction denotes a direction vertical to the power-source wiring.